CSY/reowolf Files · testdata/basic-modules/readme.txt · Centrum Wiskunde & Informatica (CWI)

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Fix bug by delaying component creation when transferred ports are blocked

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Run as:

./bin-compiler -i ./testdata/basic-modules/consumer.pdl -i ./testdata/basic-modules/producer.pdl -i ./testdata/basic-modules/main.pdl