CSY/reowolf Files · examples/eg_protocols.pdl · Centrum Wiskunde & Informatica (CWI)

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Christopher Esterhuyse

bugfix: regression from previous vers: proto components correctly enforce that each of their ports' firing variables are assigned FIRING iff that port put or get during the round

primitive pres_2(in i, out o) {
  synchronous {
    put(o, get(i));
  }
}
primitive together(in ia, in ib, out oa, out ob){
  while(true) synchronous {
    if(fires(ia)) {
      put(oa, get(ia));
      put(ob, get(ib));
    }
  }	
}

primitive alt_round_merger(in a, in b, out c){
  while(true) {
    synchronous{ put(c, get(a)); }
    synchronous{ put(c, get(b)); }
  }	
}